%PDF-1.5 %���� ºaâÚÎΞ-ÌE1ÍØÄ÷{òò2ÿ ÛÖ^ÔÀá TÎ{¦?§®¥kuµùÕ5sLOšuY
Server IP : 49.231.201.246 / Your IP : 216.73.216.149 Web Server : Apache/2.4.18 (Ubuntu) System : Linux 246 4.4.0-210-generic #242-Ubuntu SMP Fri Apr 16 09:57:56 UTC 2021 x86_64 User : root ( 0) PHP Version : 7.0.33-0ubuntu0.16.04.16 Disable Function : exec,passthru,shell_exec,system,proc_open,popen,pcntl_exec MySQL : OFF | cURL : ON | WGET : ON | Perl : ON | Python : ON | Sudo : ON | Pkexec : ON Directory : /lib/modules/4.4.0-210-generic/build/arch/sh/include/mach-common/mach/ |
Upload File : |
/* * include/asm-sh/magicpanelr2.h * * Copyright (C) 2007 Markus Brunner, Mark Jonas * * I/O addresses and bitmasks for Magic Panel Release 2 board * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. */ #ifndef __ASM_SH_MAGICPANELR2_H #define __ASM_SH_MAGICPANELR2_H #include <asm/gpio.h> #define __IO_PREFIX mpr2 #include <asm/io_generic.h> #define SETBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) | mask, reg) #define SETBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) | mask, reg) #define SETBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) | mask, reg) #define CLRBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) & ~mask, reg) #define CLRBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) & ~mask, reg) #define CLRBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) & ~mask, reg) #define PA_LED PORT_PADR /* LED */ /* BSC */ #define CMNCR 0xA4FD0000UL #define CS0BCR 0xA4FD0004UL #define CS2BCR 0xA4FD0008UL #define CS3BCR 0xA4FD000CUL #define CS4BCR 0xA4FD0010UL #define CS5ABCR 0xA4FD0014UL #define CS5BBCR 0xA4FD0018UL #define CS6ABCR 0xA4FD001CUL #define CS6BBCR 0xA4FD0020UL #define CS0WCR 0xA4FD0024UL #define CS2WCR 0xA4FD0028UL #define CS3WCR 0xA4FD002CUL #define CS4WCR 0xA4FD0030UL #define CS5AWCR 0xA4FD0034UL #define CS5BWCR 0xA4FD0038UL #define CS6AWCR 0xA4FD003CUL #define CS6BWCR 0xA4FD0040UL /* usb */ #define PORT_UTRCTL 0xA405012CUL #define PORT_UCLKCR_W 0xA40A0008UL #define INTC_ICR0 0xA414FEE0UL #define INTC_ICR1 0xA4140010UL #define INTC_ICR2 0xA4140012UL /* MTD */ #define MPR2_MTD_BOOTLOADER_SIZE 0x00060000UL #define MPR2_MTD_KERNEL_SIZE 0x00200000UL #endif /* __ASM_SH_MAGICPANELR2_H */